A logic random event is a specific change in state or a transitional state (voltage and/or current peak) at one point of the integrated circuit. Logic random events may have different origins. The consequences of a logic random event may be diverse and of variable significance. For example in a memory, a logic random event may cause the change of the contents of a memory cell, which may have to be reprogrammed in order to recover its initial value.
A logic random event is for example induced by the impact of an energetic particle at a point of the circuit. Such a random event is known as a single event upset (or SEU).
This type of random event was, up to now, primarily encountered in the integrated circuits used for space applications, because of ionizing radiation encountered outside the protective atmospheric layers of the Earth. Within the framework of earthborn applications, this type of random event is also increasingly frequent, because of the constant and gradual miniaturization of integrated circuits, which makes the latter increasingly sensitive to their environment.
The impact of an energetic particle typically causes provision of charges in the circuit, which provision generally is expressed by a voltage or current peak, at a point of the circuit corresponding to the impact point in the case of an SEU. The current or voltage change is generally of a very short duration, of the order of a few picoseconds to a few hundreds of picoseconds.
If C denotes the equivalent capacitance of the circuit downstream from the perturbed point of the circuit, then the voltage change ΔV at the relevant perturbed point is written as ΔV=ΔQ/C, ΔQ being the change in charge resulting from the impact of the particle.
Thus, for example, for a downstream logic circuit exclusively using logic signals, if the change in voltage ΔV is sufficiently small so as not to cause the change of state of a perturbed logic signal, then the perturbation disappears within a relatively short time, without any consequence for the downstream circuit.
If, on the other hand, the voltage change ΔV is larger, and notably sufficient for changing the value of a logic signal, then the consequences may be significant. A random event may thus cause latching of an inverter, reprogramming of a memory cell of the SRAM type, etc.
The voltage change due to the change in charge resulting from the impact at a point of the circuit may, therefore, not have any incidence on the circuit; or, on the contrary, it may cause a logic random event if the provided charge is larger than the critical charge of the circuit, which defines the minimum charge needed to cause the occurrence of a logic random event, i.e., a change in logic state at a point of the circuit.
Taking this phenomenon into account is particularly important in the context of circuits having a tree structure, since a random event of such a circuit may possibly have the consequence of simultaneously perturbing several components of the circuit along the branch of the circuit within a tree structure in which the random event occurs.
As an example, FIG. 1 schematically illustrates a clock circuit of an integrated circuit, formed by a tree structure comprising different branches 50-57, with which, for example, all of the components 1-16 of the integrated circuit, for example flip-flop latches, may be fed with a same initial clock signal CLK. Buffers 17-47 are generally placed along the different branches of the clock circuit to control reductions in signal level due to losses along the branches on the one hand, and phase differences generated by different branch lengths on the other hand. The buffers thus used in a clock circuit for propagating, and possibly amplifying and/or phase-shifting, a received signal generally comprise two simple inverters in series.
The consequences of a random event on a circuit such as the clock circuit of FIG. 1 may therefore be significant, since several components of the circuit may be perturbed simultaneously, along the branch of the clock circuit on which the random event occurs. For example, if a buffer 20 of the circuit is hit by an energetic particle inducing an inversion of logic state at this point of the circuit, the buffer will propagate an erroneous logic information to all of the components 1-4 connected to the terminal nodes of the clock circuit. The random event on the relevant branch of the clock circuit may, for example, cause erroneous latching of the clock signal feeding the relevant components of the integrated circuit. A first consequence for the components of the circuit using this same distributed clock signal is desynchronization of these components relative to the other components of the integrated circuit. A second consequence is the possible modification of these components: change of state of a latch, etc.
It is, therefore, desirable to protect the clock circuit of an integrated circuit against a logic random event to limit the risks of perturbation of the circuit components which use the clock signal.
The problem described here according to the example of FIG. 1 with reference to a clock circuit may, however, be extended to any integrated circuit comprising a circuit having a tree structure provided for distributing a same initial signal to a set of components of the circuit which use this initial signal for their operation. As an example, this may also be a circuit distributing a set or reset signal to a set of flip-flop latches connected at the terminal nodes of this distribution circuit; these latches may, for example, be chained so as to form a shift register.